1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory and a process of fabricating the same.
2. Description of Related Art
A variety of non-volatile semiconductor memories have been proposed, among which a typical one is disclosed by U.S. Pat. No. 4,267,632. This memory is illustrated in a schematic sectional view of FIG. 4(d).
In the non-volatile semiconductor memory shown in FIG. 4(d), a memory cell is comprised of a floating gate formed of a first polysilicon layer 13′ and bit lines 17′ located on both sides of the floating gate, and a plurality of memory cells of this structure are arranged in an array. One bit line 17′ is shared by adjacent floating gates.
The fabrication of the above-mentioned related art non-volatile semiconductor memory is explained with reference to FIG. 4(a) to 4(d).
First, as shown in FIG. 4(a), an oxide film 12 is formed on a semiconductor substrate 11 of a first conductivity type, and a first polysilicon layer 13′ is formed and patterned.
Subsequently, as shown in FIG. 4(b), bit lines 17′ are formed to have an N-type impurity and a small junction depth.
Next, as shown in FIG. 4(c), an oxide film is buried between electrodes.
Further, as shown in FIG. 4(d), an insulating film 23 is formed and a second polysilicon layer 24″ is deposited and patterned to form control gates.
Through these steps, the floating gates and the control gates are formed. Thereafter, according to an ordinary process, contact halls, aluminum electrodes and the like are formed to complete a non-volatile semiconductor memory.
FIGS. 5(a) and 5(b) show a plan view and a sectional view taken along a line A–A′ of the related art non-volatile semiconductor memory, respectively. In device isolation regions (white square regions in FIG. 5(a)) located between the control gates 24 and between the bit lines 17′, provided are impurity diffusion regions 27 (p+) of the same conductivity type as that of the substrate for improving a breakdown voltage between the bit lines 17′.
FIG. 6 shows a schematic equivalent circuit diagram of the above-described memory. Capacity 2 (Ctun) formed between the semiconductor substrate and the bit line via the oxide film around the floating gate 1 is coupled to capacity 4 (Cpp) formed between the floating gate 1 and the control gate 3 via the second insulating film.
The potential of the floating gate is controlled by capacitive coupling of the potentials of the control gate 3, the semiconductor substrate 5 and the bit lines 6a and 6b. Supposing the potential of the floating gate 1 is Vfg, that of the control gate 3 is Vcg and that of the bit lines 6a and 6b is the same as that of the semiconductor substrate 5, Vsub, for simplicity, the following equation holds:Vfg=(Vcg−Vsub)×Cpp/(Cpp+Ctun).
Defining Cpp/(Cpp+Ctun) as a gate capacitive coupling ratio Rcg (a so-called coupling ratio), the above equation is represented by Vfg=(Vcg−Vsub)×Rcg.
A capacitor which forms Cpp is composed of a lower electrode and an upper electrode. The lower electrode is the floating gate 1 separated by every bit line, and the upper electrode is the control gate 3 (a word line) separated by every bit line. Cpp is defined by the area obtained by multiplying a control gate width by the remainder of subtracting a separation width of the floating gate from the pitch of the bit lines, i.e., the area of a region where the floating gate contacts the control gate.
Ctun is defined by the area obtained by multiplying a gate length in a channel direction of the non-volatile semiconductor memory cell by a gate width in a direction perpendicular to the channel direction, i.e., the area of a region where the floating gate contacts the semiconductor substrate and the bit lines via the oxide film.
In a memory cell array (a contactless memory cell array) in which contacts for a plurality of non-volatile semiconductor memories are not positioned adjacently to the drains of the non-volatile semiconductor memories, the control gate width and a floating gate width are almost the same and restricted by the minimum photoetching dimension. For this reason, especially, the area of Ctun depends greatly upon the floating gate width in the channel direction of the non-volatile semiconductor memory cells, i.e., a channel length. That is, the smaller the floating gate width, the larger the gate capacitive coupling ratio Rcg, which means that the potential of the control gate can be controlled by applying a lower voltage and operating voltages can be reduced.
With progress of microfabrication of the non-volatile semiconductor memories, there is an increasing tendency to reduce the junction depth of the source or drain and the dimensions of an overlap of the floating gate with the source or drain.
However, since the bit line 17′ of the above-explained non-volatile semiconductor memory cell is shared with the source or drain, where the junction depth of the source or drain is reduced, the resistance of the bit line increases, and therefore, readout speed and rewrite speed slow down.
Conversely, if a higher priority is given to the reduction of the resistance of the bit line, a diffusion profile becomes greater in depth and higher in concentration, and therefore, an overlap region of the bit line with the gate, that is, an ineffective region of the non-volatile semiconductor memory increases. Consequently, it becomes difficult to reduce the size of the non-volatile semiconductor memory.
Also, as shown in FIG. 5(a), in a junction region 26 between the bit line '17 (n+) and a device isolation diffusion region 27 (p+), the impurity concentration of the bit line 17′ is raised for reducing the resistance of the bit line 17′, a sharp junction is established, and therefore, the breakdown voltage between the bit line and the semiconductor substrate is deteriorated.
Further, if the bit line is deepened for reducing its resistance, an ineffective length of the bit line, i.e., the source and drain, increases. For this reason, assuming that a prefixed gate length is to be ensured, the gate length needs to be lengthened by the ineffective length. Consequently, the capacity between the semiconductor substrate and the floating gate increases, and the above-mentioned gate capacitive coupling ratio Rcg decreases.
The increase of the ineffective length increases the capacitive coupling between the bit line and the floating gate. As a result, when the potential of the bit line serving as a drain is raised at reading or at writing, the potential of the floating gate on an unselected word line and a selected bit line is raised by the capacitive coupling due to the raised potential, which causes the leakage between the bit lines to increase.